NOSTALL=DISABLED, MASTER=SLAVE_MODE, OUTCFG=RETAIN_LASTVALUE, MATCFG=DISABLED, PCSCFG=CHIP_SELECT, PINCFG=SIN_IN_SOUT_OUT, SAMPLE=ON_SCK_EDGE, AUTOPCS=DISABLED
Configuration Register 1
| MASTER | Master Mode 0 (SLAVE_MODE): Slave mode 1 (MASTER_MODE): Master mode |
| SAMPLE | Sample Point 0 (ON_SCK_EDGE): Input data is sampled on SCK edge 1 (ON_DELAYED_SCK_EDGE): Input data is sampled on delayed SCK edge |
| AUTOPCS | Automatic PCS 0 (DISABLED): Automatic PCS generation is disabled 1 (ENABLED): Automatic PCS generation is enabled |
| NOSTALL | No Stall 0 (DISABLED): Transfers will stall when the transmit FIFO is empty 1 (ENABLED): Transfers will not stall, allowing transmit FIFO underruns to occur |
| PCSPOL | Peripheral Chip Select Polarity |
| MATCFG | Match Configuration 0 (DISABLED): Match is disabled 2 (ENABLED_FIRSTDATAMATCH): 010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1) 3 (ENABLED_ANYDATAMATCH): 011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1) 4 (ENABLED_DATAMATCH_100): 100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st data word = MATCH0) * (2nd data word = MATCH1)] 5 (ENABLED_DATAMATCH_101): 101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., [(any data word = MATCH0) * (next data word = MATCH1)] 6 (ENABLED_DATAMATCH_110): 110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)] 7 (ENABLED_DATAMATCH_111): 111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)] |
| PINCFG | Pin Configuration 0 (SIN_IN_SOUT_OUT): SIN is used for input data and SOUT is used for output data 1 (SIN_BOTH_IN_OUT): SIN is used for both input and output data, only half-duplex serial transfers are supported 2 (SOUT_BOTH_IN_OUT): SOUT is used for both input and output data, only half-duplex serial transfers are supported 3 (SOUT_IN_SIN_OUT): SOUT is used for input data and SIN is used for output data |
| OUTCFG | Output Configuration 0 (RETAIN_LASTVALUE): Output data retains last value when chip select is negated 1 (TRISTATED): Output data is tristated when chip select is negated |
| PCSCFG | Peripheral Chip Select Configuration 0 (CHIP_SELECT): PCS[3:2] are configured for chip select function 1 (HALFDUPLEX4BIT): PCS[3:2] are configured for half-duplex 4-bit transfers (PCS[3:2] = DATA[3:2]) |